Receiver circuits, like serializer/deserializer (SERDES) circuits, are becoming ubiquitous in many computational environments. The SERDES can compress a relatively wide, parallel input into a relatively narrow, serial signal (e.g., a single “bit,” differential signal) for communication over a serial bus. The serial bus switches at an appreciably higher rate than the parallel bus, and serial communication of the data stream tends to reduce cost, complexity, power, and board real estate relative to comparable parallel communications. As bus speeds increase, parallel communications manifest even higher power consumption and more issues relating to timing (e.g., skew mismatches and bit misalignment), making SERDES circuits even more attractive.
Over time, issues with the receiver circuits (e.g., and potentially also with their respective transmitter circuits, data channels, etc.) can contribute to bit errors in decoding the received signal, which can manifest as a degradation in link health. Accordingly, it is often desirable to measure link health to ensure that input/output (I/O) functions are being reliably performed. For example, in many high-speed I/O environments, techniques are used to measure the vertical size of the opening of the “data eye” as an indicator of link health. Such measurements can indicate how close a particular link is to failing (e.g., (surpassing a certain bit error rate). One traditional approach for measuring the data eye is to attach an external oscilloscope to a data pin, but such approaches can be impractical, for example, when there are large numbers of data links, or when connecting external measurement equipment is undesirable. Another traditional approach for measuring the data eye is to add dedicated circuitry to each receiver circuit (e.g., extra offset samplers to sample the data eye at different points and construct a representation of the data eye opening), but such approaches can consume additional power and additional circuit real estate, add cost and complexity to the receiver circuit design, and have other limitations.
Often, the receiver circuits include various sub-circuits that attempt to reliably extract digital data from a received signal, which can involve sampling an analog signal to derive the digital bits (i.e., ‘1’s and ‘0’s). This can involve determining where bit transitions occur and what bit value to record, often in context of noisy data, small signal levels, inter-symbol interference, and other difficult conditions. Accordingly, receiver circuits typically include various types of amplifiers, analog to digital conversion sub-circuits (e.g., data slicers), clock data recovery sub-circuits (e.g., error slicers), equalizer sub-circuits (e.g., decision feedback equalization (DFE) circuits), etc.